`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:11:08 03/17/2022 
// Design Name: 
// Module Name:    if_id 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "define.v"
module if_id(
	input wire clk,
	input wire rst,
	input wire[`InstAddrBus] if_pc,
	input wire[`InstBus]	if_inst,
	
	output reg[`InstAddrBus] id_pc,
	output reg[`InstBus] id_inst
    );
	 
	 always@(posedge clk)begin
		if(rst == `RstEnable)begin
			id_pc<=`ZeroWord;
			id_inst<=`ZeroWord;
		end else begin
			id_pc<=if_pc;
			id_inst<=if_inst;
		end
	 end


endmodule
